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vishay siliconix SI1926DL document number: 73684 s10-0792-rev. d, 05-apr-10 www.vishay.com 1 dual n-channel 60 v (d-s) mosfet product summary v ds (v) r ds(on) ( )i d (a) q g (typ.) 60 1.4 at v gs = 10 v 0.37 0.47 3.0 at v gs = 4.5 v 0.25 notes: a. based on t c = 25 c. b. surface mounted on 1" x 1" fr4 board. c. t = 5 s. d. maximum under steady stat e conditions is 400 c/w. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 60 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t c = 25 c i d 0.37 a t c = 70 c 0.30 t a = 25 c 0.34 b, c t a = 70 c 0.27 b, c pulsed drain current i dm 0.65 continuous source-drain diode current t c = 25 c i s 0.43 t a = 25 c 0.25 b, c maximum power dissipation t c = 25 c p d 0.51 w t c = 70 c 0.33 t a = 25 c 0.30 b, c t a = 70 c 0.20 b, c operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient b, d t 5 s r thja 360 415 c/w maximum junction-to-foot (drain) steady state r thjf 300 350 orderin g information: SI1926DL-t1-e3 (lead (p b )-free) SI1926DL-t1-ge3 (lead (p b )-free and halogen-free) marking code pd xx lot tracea b ility and date code part # code y y sot-363 sc-70 (6-leads) 6 4 1 2 3 5 to p v ie w s 1 g 1 d 2 d 1 g 2 s 2 n -channel mosfet g 1 d 1 s 1 n -channel mosfet g 2 d 2 s 2 features ? halogen-free according to iec 61249-2-21 definition ?trenchfet ? power mosfet ? 100 % r g te s t e d ? esd protected: 1800 v ? compliant to rohs directive 2002/95/ec applications ? low power load switch
www.vishay.com 2 document number: 73684 s10-0792-rev. d, 05-apr-10 vishay siliconix SI1926DL notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 60 v v ds temperature coefficient v ds /t j i d = 250 a 56.7 mv/c v gs(th) temperature coefficient v gs(th) /t j - 3 gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1 2.5 v gate-source leakage i gss v ds = 0 v, v gs = 10 v 150 na zero gate voltage drain current i dss v ds = 60 v, v gs = 0 v 1 a v ds = 60 v, v gs = 0 v, t j = 85 c 10 on-state drain current a i d(on) v ds = 10 v, v gs = 4.5 v 0.50 a v ds = 7.5 v, v gs = 10 v 0.65 drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 0.34 a 1.4 v gs = 4.5 v, i d = 0.23 a 3 forward transconductance g fs v ds = 30 v, i d = 0.2 a 159 ms dynamic b input capacitance c iss v ds = 30 v, v gs = 0 v, f = 1 mhz 18.5 pf output capacitance c oss 7.5 reverse transfer capacitance c rss 4.2 total gate charge q g v ds = 30 v, v gs = 10 v, i d = 0.34 a 0.9 1.4 nc v ds = 30 v, v gs = 4.5 v, i d = 0.34 a 0.5 0.75 gate-source charge q gs 0.2 gate-drain charge q gd 0.15 gate resistance r g f = 1 mhz 160 240 tu r n - o n d e l ay t i m e t d(on) v dd = 30 v, r l = 100 i d ? 0.3 a, v gen = 10 v, r g = 1 6.5 10 ns rise time t r 12 18 turn-off delaytime t d(off) 13 22 fall time t f 14 21 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c 0.43 a pulse diode forward current a i sm 0.65 body diode voltage v sd i s = 0.3 a 0.8 1.2 v body diode reverse recovery time t rr i f = 0.6 a, di/dt = 100 a/s 16.5 25 nc body diode reverse recovery charge q rr 13 20 ns reverse recovery fall time t a 13.5 reverse recovery rise time t b 3
document number: 73684 s10-0792-rev. d, 05-apr-10 www.vishay.com 3 vishay siliconix SI1926DL typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current gate charge 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0 .7 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v gs = 10 v thr u 5 v v ds - drain-to-so u rce v oltage ( v ) ) a ( t n e r r u c n i a r d - i d v gs = 4 v v gs = 3 v 0.0 0.5 1.0 1.5 2.0 2.5 3 . 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 v gs = 4.5 v i d - drain c u rrent (a) v gs = 10 v r ) n o ( s d ( e c n a t s i s e r - n o -) 0 2 4 6 8 10 0.0 0.3 0.6 0.9 1.2 i d = 0.5 a ) v ( e g a t l o v e c r u o s - o t - e t a g - q g - total gate charge (nc) v s g v ds = 30 v v ds = 4 8 v transfer characteristics curves vs. temperature capacitance on-resistance vs. junction temperature 0.0 0.1 0.2 0.3 0 . 4 01234 v gs - gate-to-so u rce v oltage ( v ) ) a ( t n e r r u c n i a r d - i d t c = 25 c t c = - 55 c t c = 125 c 0 8 16 24 32 0 102030405060 c rss v ds - drain-so u rce v oltage ( v ) ) f p ( e c n a t i c a p a c - c c oss c iss 0.6 0. 8 1.0 1.2 1.4 1 . 6 - 50 - 25 0 25 50 75 100 125 150 v gs = 10 v , i d = 0.5 a t j - j u nction temperat u re (c) r ) n o ( s d e c n a t s i s e r - n o - ) d e z i l a m r o n ( v gs = 4.5 v , i d = 0.2 a
www.vishay.com 4 document number: 73684 s10-0792-rev. d, 05-apr-10 vishay siliconix SI1926DL typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 1 10 100 1000 0.0 0.3 0.6 0.9 1.2 1.5 v sd - so u rce-to-drain v oltage ( v ) ) a ( t n e r r u c e c r u o s - i s t a = 150 c t a = 25 c 1.0 1.2 1.4 1.6 1. 8 2 . 0 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a v ( v ) ) h t ( s g t j - temperat u re (c) r ds(on) vs. v gs vs. temperature single pulse power 0.0 1.0 2.0 3.0 4.0 5. 0 34567 8 9 10 v gs - gate-to-so u rce v oltage ( v ) t a = 25 c t a = 125 c r ) n o ( s d ( e c n a t s i s e r - n o -) i d = 0.5 a 0 3 5 1 2 ) w ( r e w o p time (s) 4 1 100 600 10 10 -1 10 -2 10 -3 safe operating area ) a ( t n e r r u c n i a r d - i d 10 s t a = 25 c single p u lse dc v ds - drain-to-so u rce v oltage ( v ) * v gs minim u m v gs at w hich r ds(on) is specified 0.001 0.01 0.1 1 0.1 1 10 100 limited b y r * ds(on) 1 s 100 ms 10 ms b v dss limited
document number: 73684 s10-0792-rev. d, 05-apr-10 www.vishay.com 5 vishay siliconix SI1926DL typical characteristics 25 c, unless otherwise noted * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resi stance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determ ine the current rating, when this rating falls below the package limit. current derating* 0.0 0.1 0.2 0.3 0.4 0 .5 0 25 50 75 100 125 150 i d ) a ( t n e r r u c n i a r d - t c - case temperat u re (c) power derating 0.0 0.1 0.2 0.3 0.4 0 .5 0 25 50 75 100 125 150 t c - case temperat u re (c) ) w ( n o i t a p i s s i d r e w o p
www.vishay.com 6 document number: 73684 s10-0792-rev. d, 05-apr-10 vishay siliconix SI1926DL typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73684 . normalized thermal transient impedance, junction-to-ambient 10 -3 10 -2 110 600 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) t n e i s n a r t e v i t c e f f e d e z i l a m r o n e c n a d e p m i l a m r e h t 1. d u ty cycle, d = 2. per unit base = r thja = 400 c/ w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 110 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) t n e i s n a r t e v i t c e f f e d e z i l a m r o n e c n a d e p m i l a m r e h t
l c e e 1 e d e 1 a 2 a a 1 1 -a- b -b- 23 654 package information vishay siliconix document number: 71154 06-jul-01 www.vishay.com 1

dim min nom max min nom max a 0.90 ? 1.10 0.035 ? 0.043 a 1 ? ? 0.10 ? ? 0.004 a 2 0.80 ? 1.00 0.031 ? 0.039 b 0.15 ? 0.30 0.006 ? 0.012 c 0.10 ? 0.25 0.004 ? 0.010 d 1.80 2.00 2.20 0.071 0.079 0.087 e 1.80 2.10 2.40 0.071 0.083 0.094 e 1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65bsc 0.026bsc e 1 1.20 1.30 1.40 0.047 0.051 0.055 l 0.10 0.20 0.30 0.004 0.008 0.012 7 nom 7 nom ecn: s-03946?rev. b, 09-jul-01 dwg: 5550
an814 vishay siliconix document number: 71237 12-dec-03 www.vishay.com 1 dual-channel little foot sc-70 6-pin mosfet recommended pad pattern and thermal performance introduction this technical note discusses the pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for dual-channel little foot power mosfets in the sc-70 package. these new v ishay siliconix devices are intended for small-signal applications where a miniaturized package is needed and low levels of current (around 250 ma) need to be switched, either directly or by using a level shift configuration. v ishay provides these devices with a range of on-resistance specifications in 6-pin versions. the new 6-pin sc-70 package enables improved on-resistance values and enhanced thermal performance. pin-out figure 1 shows the pin-out description and pin 1 identification for the dual-channel sc-70 device in the 6-pin configuration. figure 1. sot-363 sc-70 (6-leads) 6 4 1 2 3 5 top view s 1 g 1 d 2 d 1 g 2 s 2 for package dimensions see outline drawing sc-70 (6-leads) ( http://www.vishay.com/doc?71154 ) basic pad patterns see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ) for the 6-pin sc-70. this basic pad pattern is sufficient for the low-power applications for which this package is intended. for the 6-pin device, increasing the pad patterns yields a reduction in thermal resistance on the order of 20% when using a 1-inch square with full copper on both sides of the printed circuit board (pcb). evaluation boards for the dual sc70-6 the 6-pin sc-70 evaluation board (evb) measures 0.6 inches by 0.5 inches. the copper pad traces are the same as described in the previous section, basic pad patterns . the board allows interrogation from the outer pins to 6-pin dip connections permitting test sockets to be used in evaluation testing. the thermal performance of the dual sc-70 has been measured on the evb with the results shown below. the minimum recommended footprint on the evaluation board was compared with the industry standard 1-inch square fr4 pcb with copper on both sides of the board. thermal performance junction-to-foot thermal resistance (the package performance) thermal performance for the dual sc-70 6-pin package measured as junction-to-foot thermal resistance is 300 c/w typical, 350 c/w maximum. the ?foot? is the drain lead of the device as it connects with the body. note that these numbers are somewhat higher than other little foot devices due to the limited thermal performance of the alloy 42 lead-frame compared with a standard copper lead-frame. junction-to-ambient thermal resistance (dependent on pcb size) the typical r ja for the dual 6-pin sc-70 is 400 c/w steady state. maximum ratings are 460 c/w for the dual. all figures based on the 1-inch square fr4 test board. the following example shows how the thermal resistance impacts power dissipation for the dual 6-pin sc-70 package at two different ambient temperatures.
an814 vishay siliconix www.vishay.com 2 document number: 71237 12-dec-03 sc-70 (6-pin) room ambient 25 c elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 25 o c 400 o c w p d 312 mw p d t j(max) t a r ja p d 150 o c 60 o c 400 o c w p d 225 mw note: although they are intended for low-power applications, devices in the 6-pin sc-70 will handle power dissipation in excess of 0.2 w. testing to aid comparison further, figure 2 illustrates the dual-channel sc-70 thermal performance on two different board sizes and two different pad patterns. the results display the thermal performance out to steady state. the measured steady state values of r ja for the dual 6-pin sc-70 are as follows: little foot sc-70 (6-pin) 1) minimum recommended pad pattern (see figure 2) on the evb of 0.5 inches x 0.6 inches. 518 c/w 2) industry standard 1? square pcb with maximum copper both sides. 413 c/w time (secs) figure 2. comparison of dual sc70-6 on evb and 1? square fr4 pcb. thermal resistance (c/w) 0 1 500 100 200 100 1000 300 10 10 -1 10 -2 10 -3 10 -4 10 -5 1? square fr4 pcb dual evb 400 the results show that if the board area can be increased and maximum copper traces are added, the thermal resistance reduction is limited to 20%. this fact confirms that the power dissipation is restricted with the package size and the alloy 42 leadframe. associated document single-channel little foot sc-70 6-pin mosfet copper leadframe version, recommended pad pattern and thermal performance, an815, (http://www.vishay.com/doc?71334) .
application note 826 vishay siliconix www.vishay.com document number: 72602 18 revision: 21-jan-08 application note recommended minimum pads for sc-70: 6-lead 0.096 (2.438) recommended mi nimum pads dimensions in inches/(mm) 0.067 (1.702) 0.026 (0.648) 0.045 (1.143) 0.016 (0.406) 0.026 (0.648) 0.010 (0.241) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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